1. Field of the Invention
The present invention relates to a semiconductor device having a plurality of elemental active devices such as field effect transistors capable of being operated by two or more different voltages, and relates to a method for fabricating the same.
2. Related Background Art
FIG. 1A shows a sectional view of a conventional type of semiconductor device having two different active devices and, more specifically, shows a sectional view of an inverter circuit constituted by two types of heterojunction field effect transistors (to be referred to as FETs hereinafter). As shown in FIG. 1A, a nondoped GaAs layer 2, an n-type AlGaAs layer 3 having a smaller electron affinity than that of the nondoped GaAs layer 2 and containing a donor impurity, and an n-type GaAs layer 4 are formed on a semi-insulating GaAs substrate 1. The n-type GaAs layer 4 and the n-type AlGaAs layer 3 are partially etched, and gate electrodes 5 are formed. Source and drain electrodes 6 are then formed on the n-type GaAs layer 4, and wirings 8 are formed thereon through an insulating film 7.
A gate threshold voltage of a heterojunction FET is generally determined by the impurity concentration and thickness of the n-type AlGaAs layer under the gate electrode. In an illustrated inverter circuit, in order to form an enhancement mode (to be referred to as an E mode hereinafter) FET and a depletion mode (to be referred to as a D mode hereinafter) FET on a single substrate, the thickness of the AlGaAs layer 3 is changed depending on the region for forming an E or D mode FET element. More specifically, by changing the thickness of the active layer consisting of AlGaAs, FETs having different threshold voltages can be formed on a single substrate. In this case, recess (groove) etching must be repeated twice in the gate electrode formation step, thus complicating the formation process. Etching methods include wet etching and dry etching. Even if either technique is used, it is difficult to accurately perform recess etching for different depths with good reproducibility.
Japanese Patent Laid-Open No. 60-116178 discloses another conventional semiconductor device consisting of E and D mode FETs being operable with different threshold voltages. The technique for fabricating this semiconductor device will be briefly described below. An AlGaAs layer is formed to have a thickness corresponding to a difference between E and D mode n-type AlGaAs layers. Prior to recess etching, a prospective gate electrode formation region of the E mode FET is selectively removed, and the gate electrode formation step is performed simultaneously for the E and D mode FET elements. According to this technique, however, the step of selectively removing a narrow region of the prospective gate electrode formation region of the E mode FET with good reproducibility is increased, resulting in the complicated process.
In addition, Solid-State Device Conference (1984), pp. 359 to 362 discloses another conventional semiconductor device. In the technique for fabricating this semiconductor device, an etching stopper layer is provided to form an E mode high electron mobility transistor (to be referred to as an HEMT hereinafter) and a D mode HEMT on a single substrate. This technique will be briefly described with reference to FIG. 1B. A nondoped GaAs layer 12, an Si-doped AlGaAs layer 13, upper layers 14, 15, and 16 are epitaxially grown on a semi-insulating GaAs substrate 11 by molecular beam epitaxy (to be referred to as MBE hereinafter). The upper layers are constituted by the GaAs layers 14 and 16, and the AlGaAs etching stopper layer 15 formed between them. The upper layers 14, 15, and 16 and the AlGaAs layer 13 are partially and selectively etched, and gate electrodes 20 are formed. Source and drain electrodes 21 are then formed on the GaAs layer 16, and wirings 19 are then formed thereon through insulating films 17 and 18 consisting of SiO.sub.2.
According to this technique, however, a crystal growth time is undesirably prolonged, and any one of the areas must be exposed prior to formation of the gate electrodes, thereby increasing high-precision steps with good reproducibility and complicating the fabrication process.
Farther, there is no method of easily forming a semiconductor device having three or more types of active devices being operable with different threshold voltages on a single semiconductor substrate. When active devices having three or more threshold voltages are forcibly formed on a single semiconductor substrate, the thicknesses of active layers must be changed in accordance with types of active device. Therefore, the above complicated methods must be combined to perform recess etching of the high-precision active layers three times or more with good reproducibility.